Define the Non-Secure timer frame ID for ARM platforms

On Juno and FVP platforms, the Non-Secure System timer corresponds
to frame 1. However, this is a platform-specific decision and it
shouldn't be hard-coded. Hence, this patch introduces
PLAT_ARM_NSTIMER_FRAME_ID which should be used by all ARM platforms
to specify the correct non-secure timer frame.

Change-Id: I6c3a905d7d89200a2f58c20ce5d1e1d166832bba

diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index e5005b9a60a359ef5e4900d0468ab353f5446fc7..38ff9ddd7df81bf3b7a44ce35fd48655e0b2f453 100644 (file)
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -113,4 +113,7 @@
 #define PLAT_ARM_TZC_FILTERS           REG_ATTR_FILTER_BIT_ALL
 #define PLAT_ARM_TZC_BASE              0x2a4a0000
 
+/* System timer related constants */
+#define PLAT_ARM_NSTIMER_FRAME_ID      1
+
 #endif /* __CSS_DEF_H__ */

diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 9f42fd26f68520c20f03870e7a6e3bddc8bc69ff..155216a8a412a3360afe1e2768d3a2e938789189 100644 (file)
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -85,6 +85,9 @@
 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX      3
 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX      4
 
+/* System timer related constants */
+#define PLAT_ARM_NSTIMER_FRAME_ID              1
+
 /* TrustZone controller related constants
  *
  * Currently only filters 0 and 2 are connected on Base FVP.

diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 3fda2ef85367a00363c09a290eb2eea80b4aefda..899463ee95421358db7de3cb05217a1b7bc54971 100644 (file)
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -40,6 +40,7 @@
 #include <mmio.h>
 #include <plat_arm.h>
 #include <platform.h>
+#include <platform_def.h>
 
 
 /*
@@ -219,9 +220,9 @@ void arm_bl31_platform_setup(void)
        reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
        reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
        reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
-       mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
+       mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
 
-       reg_val = (1 << CNTNSAR_NS_SHIFT(1));
+       reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
        mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
 
        /* Initialize power controller before setting up topology */